In many electronic systems, it is necessary to generate an output signal that, while synchronized with a system clock signal, is generated based on two or more input signals that are asynchronous to the system clock signal. By "asynchronous", it is meant that these input signals have no predictable relationship to the system clock signal. Many prior art systems can perform this operation, but their solutions generally involves introducing what for some applications is an intolerable delay. In particular, in some applications, it is required that the synchronized output signal be generated within no more than a half period of the system clock duty cycle.